Electronic odometers for automotive vehicles are generally required to store input pulses for the life of the vehicle operation. To assure a permanent record of vehicle usage, even in the event of power loss to the odometer, nonvolatile memories are used. In addition, high resolution is necessary. For example it is desired to store data representing each 0.1 mile of travel. Thus very large numbers of input pulses must be counted and retained without danger of loss. Standard binary counters are able to efficiently store large numbers but such counters utilizing nonvolatile memories are subject to wearing out through repeated erase and write operations.
A traditional scheme for avoiding the high incidence of erase and write operations is to use a volatile memory counter for normal operation and to write the counter contents to a nonvolatile memory only when a loss of power is impending. This requires circuits to detect such power loss, to interrupt normal counting, and to carry out the storage activity. Alternatively, only volatile counters are used for low order registers but battery back-up for the volatile counters is expensive and can drain vehicle batteries over extended periods of nonuse.
Another way of using nonvolatile memories in odometers is to provide a large number of redundant memories for the low order register to distribute the wear caused by the frequent updating of the low order data. The redundant locations are swapped with each other to provide a longer effective life. For example, if 24 bits of data (3 eight bit words) are to be stored in a conventional binary format it can record 128,000 miles with a resolution of 0.1 mile if the second word is limited to 10,000 writes or erasures. It is assumed that 10,000 writes or erasures can be made to the memories yielding an acceptable life span. The two higher order 8 bit words do not require any redundancy since they will not be written to more than 10,000 times. However the lower word will undergo 1.28 million erase/write sequences. To insure that no location is written or erased more than 10,000 times, 128 redundant banks of 8 bit memory or 1024 bits are required to share the load. In addition to the storage locations, logic must be provided to perform read, write and erase operations in individual banks as well as logic to select which banks are to be currently used.
It has further been proposed, as described in the U.S. Pat. No. 4,682,287 to Mizuno et al., to use nonvolatile memories which are linearly arranged to be written to bit by bit in sequence. A first memory has 256 cells and the second memory has 32 cells. Each input pulse represents 1 km and causes a "1" to be written to one of the cells so that the first memory can accumulate 256 km, while each cell is written only once, thereby reducing the frequency of erase/write operations. When the first memory is full it is erased and the second memory is incremented by placing a "1" in one of its cells so that each digit in the second memory represents 256 km. The total memory capacity is (256.times.32)+256 so that only 8448 km can be stored with the recommended memory sizes and only a resolution of 1 km is offered. In addition, the control of the memory requires a microcomputer or other complex logic circuits.